Embodiments of the inventive concept relate generally to a semiconductor memory device. More particularly, embodiments of the inventive concept relate to a semiconductor memory device capable of compensating for differences in data signal delays occurring in a data training mode of the device and those occurring in a normal operating mode of the device.
Data is transmitted between a semiconductor memory device and a memory controller in synchronization with a clock signal output by the memory controller. During these data transmissions, the relative timing of both the data signals and the clock signal may become skewed due to a number of factors such as interference between adjacent signal lines. To address these timing effects, data training operations may be performed on the relevant transmission pathways so that appropriate compensating adjustments can be made to the timing during normal operation of the semiconductor device. The data training may involve, for instance, characterization of the timing skew, including recognition of data patterns associated with certain types of skew, and development of compensation patterns.
Unfortunately, the operating environment or chip status in which the training is performed may be different from the normal operating environment or chip status of the semiconductor memory device. As a result, the compensation patterns developed during training may be different from those required under normal operating conditions. Accordingly, timing errors may arise when the compensation patterns are applied under normal operating conditions.